Verification Engineer IV

Immediate need for a talented Verification Engineer IV. This is a 06+ Months Contract opportunity with long-term potential and is located in Sunnyvale, CA(Hybrid). Please review the job description below and contact me ASAP if you are interested.

Job ID:25-69328

Pay Range: $80 - $83/hour.  Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
 
Key Responsibilities:

• Define electrical verification methodologies for each of the different systems by working with researchers, architects, and the design teams
• Define and track detailed test plans for the different modules and top-level systems
• Define, architect, design, and drive implementation of scalable test infrastructure
• Create and enhance constraine-random verification environments using system Verilog and universal verification methodology(UVM) and track progress with coverage closure.
• Own execution, interpretation, and reporting of electrical system level verification work status and results.

Key Requirements and Technology Experience:

• Skills-Verification methodologies, UVM and System Verilog.
• Hands on coding skill in SV/UVM. Strong System Verilog, debugging skills, experience owning areas of product verification.
• 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog.
• Working knowledge of C#, Python, and LabVIEW.

Our client is a leading Meta Industry and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration.
 
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