Design Engineer V - Power ASIC Engineer

Immediate need for a talented Design Engineer V - Power ASIC Engineer. This is a 06 Months Contract opportunity with long-term potential and is located in Sunnyvale, CA (Hybrid). Please review the job description below and contact me ASAP if you are interested.

Job ID:26-09310

Pay Range: $100 - $105/hour.  Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
 
Key Responsibilities:

• Perform PPA optimization with Fusion compiler.
• Perform RTL and netlist level Power analysis
• Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction
• Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)
• Implement some blocks at RTL and UPF
• Ability to document and communicate clearly

Key Requirements and Technology Experience:

• Must have skills: -"Prime power", "power Artist" and "ASIC"
• 10 Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer
• Experience with power estimation tools and synthesis, some physical design
• Experience with Synopsys (DC, ICC, PTPX/Prime Power, VCS, Verdi) and/or Cadence (Joules)
• Should know how to use Python, Perl (or similar) scripting and data-post-processing tools
• Experience in low power design, tools and methodologies including power intent UPF specifications
• Knowledge of power trade-offs in design and back end implementation
• Hands-on experience in scripting, data analysis
• BS in Electrical Engineering/Computer Science or equivalent experience

Our client is a leading Social Media Industry and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration.
 
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